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TI / Nexperia / many · Integrated circuit

74HC138 3-to-8 Decoder

Three address lines in, one of eight outputs low. The standard way to generate chip selects in a homebrew computer.

Cheat sheet (SVG)
Logic level
2-6 V (HC)
Package
PDIP-16 / SOIC-16

1.Pinout diagram

Highlight a signalhover to preview, click to keep

Pins 1-8

74HC138

Pins 9-16

Pin detail

Hover a pin for its mappings and gotchas. Click to keep it here.

Logic level
2-6 V (HC)
Package
PDIP-16 / SOIC-16

Fig. 1. 74HC138 3-to-8 Decoder, PDIP-16. Hover or tap a signal to light up every pin that carries it.

2.Watch out

  • Outputs are ACTIVE LOW. Exactly one of Y0 to Y7 goes low, the rest stay high, which is exactly what an active-low chip select wants.
  • Three enables, and all three must agree: E1 and E2 are active low, E3 is active high. That is deliberate, because it lets you gate the decoder with the CPU clock and an address line without extra gates. On a 6502, E3 from PHI2 and E1 from a high address bit is the whole decode.
  • Cascade two by feeding a fourth address bit into E3 of one and an inverted copy into E2 of the other, which gives you 4-to-16 without a bigger part.
  • Leaving any enable floating means the decoder either never fires or fires constantly. This is the usual reason a breadboard bus has two devices driving at once.
  • For 4-to-16 in one package the 74HC154 does it directly, at 24 pins.

3.Minimum circuit

What has to go around the chip before it will run.

VCCGND74HC138Wire link between E1 (4) and GNDWire linkWire link between E2 (5) and GNDWire linkWire link between E3 (6) and VCCWire link100 nF between VCC (16) and GND100 nFGND (8) to GNDVCC (16) to VCCE1 4E2 5E3 6GND 8VCC 16VCC 16
Fig. 2. Minimum circuit, drawn from Table 1. Crossing wires are not connected.
Table 1. External parts, and why each one is there.
PartBetween
Wire linkE1 (4) to GND
Wire linkE2 (5) to GND
Wire linkE3 (6) to VCC
100 nFVCC (16) to GND

The outputs are active low: the selected one goes low and the other seven stay high. Feed a real address line into an enable rather than tying it, and the decoder does the chip selecting for a whole bus.

4.Full pin reference

Every pin, alias and mapping. This is the table that prints.

Table 2. Pin assignments.

Complete pin reference for 74HC138 3-to-8 Decoder
PinNameFunctions

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Primary sources

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