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TI / Nexperia / many · Integrated circuit

74HC32 Quad OR Gate

Four 2-input OR gates, in the same pin arrangement as the 74HC00 and 74HC08.

Cheat sheet (SVG)
Logic level
2-6 V (HC)
Package
PDIP-14 / SOIC-14

1.Pinout diagram

Highlight a signalhover to preview, click to keep

Pins 1-7

74HC32

Pins 8-14

Pin detail

Hover a pin for its mappings and gotchas. Click to keep it here.

Logic level
2-6 V (HC)
Package
PDIP-14 / SOIC-14

Fig. 1. 74HC32 Quad OR Gate, PDIP-14. Hover or tap a signal to light up every pin that carries it.

2.Watch out

3.Minimum circuit

What has to go around the chip before it will run.

VCCGND74HC32Wire link between 1B (2) and GNDWire linkWire link between 4A (12) and GNDWire linkWire link between 4B (13) and GNDWire link100 nF between VCC (14) and GND100 nFGND (7) to GNDVCC (14) to VCC1B 2GND 74A 124B 13VCC 14VCC 14
Fig. 2. Minimum circuit, drawn from Table 1. Crossing wires are not connected.
Table 1. External parts, and why each one is there.
PartBetween
Wire link1B (2) to GND
Wire link4A (12) to GND
Wire link4B (13) to GND
100 nFVCC (14) to GND

On an OR gate an unused input must go low, not high: tie it high and the output is stuck at 1 forever. The opposite of the rule for an AND gate.

4.Full pin reference

Every pin, alias and mapping. This is the table that prints.

Table 2. Pin assignments.

Complete pin reference for 74HC32 Quad OR Gate
PinNameFunctions

Found a wrong pin? The whole board is one file, data/boards/sn74hc32.json.

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