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TI / Nexperia / many · Integrated circuit

74HC86 Quad XOR Gate

Four 2-input XOR gates: a controlled inverter, a one-bit comparator and the core of every adder and CRC.

Cheat sheet (SVG)
Logic level
2-6 V (HC)
Package
PDIP-14 / SOIC-14

1.Pinout diagram

Highlight a signalhover to preview, click to keep

Pins 1-7

74HC86

Pins 8-14

Pin detail

Hover a pin for its mappings and gotchas. Click to keep it here.

Logic level
2-6 V (HC)
Package
PDIP-14 / SOIC-14

Fig. 1. 74HC86 Quad XOR Gate, PDIP-14. Hover or tap a signal to light up every pin that carries it.

2.Watch out

3.Controlled inverter

What has to go around the chip before it will run.

VCCGND74HC86Wire link between 1B (2) and VCCWire linkWire link between 4A (12) and GNDWire linkWire link between 4B (13) and GNDWire link100 nF between VCC (14) and GND100 nFGND (7) to GNDVCC (14) to VCC1B 2GND 74A 124B 13VCC 14VCC 14
Fig. 2. Controlled inverter, drawn from Table 1. Crossing wires are not connected.
Table 1. External parts, and why each one is there.
PartBetween
Wire link1B (2) to VCC
Wire link4A (12) to GND
Wire link4B (13) to GND
100 nFVCC (14) to GND

A switchable inverter is most of why an XOR is on a board at all, that and parity. Four of them in a row make a one-instruction NOT across a nibble.

4.Full pin reference

Every pin, alias and mapping. This is the table that prints.

Table 2. Pin assignments.

Complete pin reference for 74HC86 Quad XOR Gate
PinNameFunctions

Found a wrong pin? The whole board is one file, data/boards/sn74hc86.json.

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